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The future of CMOS device reliability assessment: from individual traps to circuit simulations

dc.contributor.authorGroeseneken, Guido
dc.contributor.authorKaczer, Ben
dc.contributor.authorToledano Luque, Maria
dc.contributor.authorFranco, Jacopo
dc.contributor.authorRoussel, Philippe
dc.date.accessioned2021-10-20T11:20:20Z
dc.date.available2021-10-20T11:20:20Z
dc.date.issued2012
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20753
dc.sourceIIOimport
dc.titleThe future of CMOS device reliability assessment: from individual traps to circuit simulations
dc.typeOral presentation
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorFranco, Jacopo
dc.contributor.imecauthorRoussel, Philippe
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecFranco, Jacopo::0000-0002-7382-8605
dc.contributor.orcidimecRoussel, Philippe::0000-0002-0402-8225
dc.source.peerreviewno
dc.source.conferenceChina Semiconductor Technology International Conference - CSTIC
dc.source.conferencedate18/03/2012
dc.source.conferencelocationShanghai China
imec.availabilityPublished - imec


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