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Process development to enable die sorting and 3D IC stacking

dc.contributor.authorLa Manna, Antonio
dc.contributor.authorDaily, Robert
dc.contributor.authorCapuz, Giovanni
dc.contributor.authorRebibis, Kenneth June
dc.contributor.authorBogaerts, Lieve
dc.contributor.authorMiller, Andy
dc.contributor.authorBeyne, Eric
dc.date.accessioned2021-10-20T12:28:34Z
dc.date.available2021-10-20T12:28:34Z
dc.date.issued2012-12
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20973
dc.sourceIIOimport
dc.titleProcess development to enable die sorting and 3D IC stacking
dc.typeProceedings paper
dc.contributor.imecauthorLa Manna, Antonio
dc.contributor.imecauthorCapuz, Giovanni
dc.contributor.imecauthorRebibis, Kenneth June
dc.contributor.imecauthorBogaerts, Lieve
dc.contributor.imecauthorMiller, Andy
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecCapuz, Giovanni::0000-0002-5263-4836
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.source.peerreviewyes
dc.source.conference14th Electronics Packaging Technology Conference - EPTC
dc.source.conferencedate5/12/2012
dc.source.conferencelocationSingapore
imec.availabilityPublished - imec


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