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Electrical characterization method to study barrier integrity in 3D through-silicon vias

dc.contributor.authorLi, Yunlong
dc.contributor.authorVelenis, Dimitrios
dc.contributor.authorKauerauf, Thomas
dc.contributor.authorStucchi, Michele
dc.contributor.authorCivale, Yann
dc.contributor.authorRedolfi, Augusto
dc.contributor.authorCroes, Kristof
dc.date.accessioned2021-10-20T12:44:34Z
dc.date.available2021-10-20T12:44:34Z
dc.date.issued2012
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21021
dc.sourceIIOimport
dc.titleElectrical characterization method to study barrier integrity in 3D through-silicon vias
dc.typeProceedings paper
dc.contributor.imecauthorLi, Yunlong
dc.contributor.imecauthorVelenis, Dimitrios
dc.contributor.imecauthorStucchi, Michele
dc.contributor.imecauthorRedolfi, Augusto
dc.contributor.imecauthorCroes, Kristof
dc.contributor.orcidimecLi, Yunlong::0000-0003-4791-4013
dc.contributor.orcidimecCroes, Kristof::0000-0002-3955-0638
dc.source.peerreviewyes
dc.source.conference62nd Electronic Components and Technology Conference - ECTC
dc.source.conferencedate29/05/2012
dc.source.conferencelocationSan Diego, CA USA
imec.availabilityPublished - imec


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