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ESD consideration on 3D stacking integrated circuits constructed with through-silicon-via (TSV) and micro-bump structures

dc.contributor.authorLinten, Dimitri
dc.contributor.authorChen, Shih-Hung
dc.date.accessioned2021-10-20T12:49:30Z
dc.date.available2021-10-20T12:49:30Z
dc.date.issued2012-07
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21035
dc.sourceIIOimport
dc.titleESD consideration on 3D stacking integrated circuits constructed with through-silicon-via (TSV) and micro-bump structures
dc.typeMeeting abstract
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.source.peerreviewno
dc.source.conferenceSematech 3D interconnect workshop: ESD challenges for 3d ICs
dc.source.conferencedate10/07/2012
dc.source.conferencelocationSan Francisco, CA USA
imec.availabilityPublished - imec


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