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Extension of a 3D-DfT architecture for embedded cores and multiple towers

dc.contributor.authorPapameletis, Christos
dc.contributor.authorChickermane, Vivek
dc.contributor.authorKeller, Brion
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-20T14:14:58Z
dc.date.available2021-10-20T14:14:58Z
dc.date.issued2012
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21254
dc.sourceIIOimport
dc.titleExtension of a 3D-DfT architecture for embedded cores and multiple towers
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.conferenceIEEE International Workshop on Testing Three-Dimensional Stacked ICs - 3D-TEST
dc.source.conferencedate8/11/2012
dc.source.conferencelocationAnaheim, CA USA
imec.availabilityPublished - imec


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