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Test strategies for wide-I/O memory, 3D-TSV technology test vehicles and ultra-fine-pitch applications

dc.contributor.authorSmith, Ken
dc.contributor.authorBock, Daniel
dc.contributor.authorGleeson, Read
dc.contributor.authorJolley, Mike
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-20T16:15:36Z
dc.date.available2021-10-20T16:15:36Z
dc.date.issued2012-11
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21525
dc.sourceIIOimport
dc.titleTest strategies for wide-I/O memory, 3D-TSV technology test vehicles and ultra-fine-pitch applications
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.conferenceIEEE International Workshop on Testing Three-Dimensional Stacked ICs - 3D-TEST
dc.source.conferencedate8/11/2012
dc.source.conferencelocationAnaheim, CA USA
imec.availabilityPublished - imec


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