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Test impact on the overall die-to-wafer 3D stacked IC cost

dc.contributor.authorTaouil, Mottaqiallah
dc.contributor.authorHamdioui, Said
dc.contributor.authorBeenakker, Kees
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-20T16:48:05Z
dc.date.available2021-10-20T16:48:05Z
dc.date.issued2012-02
dc.identifier.issn0923-8174
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21593
dc.sourceIIOimport
dc.titleTest impact on the overall die-to-wafer 3D stacked IC cost
dc.typeJournal article
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.beginpage15
dc.source.endpage25
dc.source.journalJournal of Electronic Testing - Theory and Applications (JETTA)
dc.source.issue1
dc.source.volume28
dc.identifier.urlhttp://dx.doi.org/10.1007/s10836-011-5270-3
imec.availabilityPublished - imec


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