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dc.contributor.authorVaglio Pret, Alessandro
dc.contributor.authorPoliakov, Pavel
dc.contributor.authorGronheid, Roel
dc.contributor.authorBlomme, Pieter
dc.contributor.authorMiranda Corbalan, Miguel
dc.contributor.authorDehaene, Wim
dc.contributor.authorVerkest, Diederik
dc.contributor.authorVan Houdt, Jan
dc.contributor.authorBianchi, Davide
dc.date.accessioned2021-10-20T17:23:38Z
dc.date.available2021-10-20T17:23:38Z
dc.date.issued2012
dc.identifier.issn0167-9317
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21664
dc.sourceIIOimport
dc.titleLinking EUV lithography line edge roughness and 16 nm NAND memory performance
dc.typeJournal article
dc.contributor.imecauthorVaglio Pret, Alessandro
dc.contributor.imecauthorGronheid, Roel
dc.contributor.imecauthorBlomme, Pieter
dc.contributor.imecauthorDehaene, Wim
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.source.peerreviewyes
dc.source.beginpage24
dc.source.endpage28
dc.source.journalMicroelectronic Engineering
dc.source.issue10
dc.source.volume98
dc.identifier.urlhttp://www.sciencedirect.com/science/article/pii/S0167931712001700
imec.availabilityPublished - imec


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