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Back bias influence on analog performance of pTFET

dc.contributor.authorAgopian, P.G.D.
dc.contributor.authorNeves, F.S.
dc.contributor.authorMartino, J.A.
dc.contributor.authorVandooren, Anne
dc.contributor.authorRooyackers, Rita
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-21T06:42:06Z
dc.date.available2021-10-21T06:42:06Z
dc.date.issued2013
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21954
dc.sourceIIOimport
dc.titleBack bias influence on analog performance of pTFET
dc.typeProceedings paper
dc.contributor.imecauthorVandooren, Anne
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecVandooren, Anne::0000-0002-2412-0176
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage9a.4
dc.source.conferenceIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
dc.source.conferencedate7/10/2013
dc.source.conferencelocationMonterey, CA USA
imec.availabilityPublished - open access


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