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Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs

dc.contributor.authorDeutsch, Sergej
dc.contributor.authorChakrabarty, Krishnendu
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-21T07:18:21Z
dc.date.available2021-10-21T07:18:21Z
dc.date.issued2013-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/22259
dc.sourceIIOimport
dc.titleUncertainty-aware robust optimization of test-access architectures for 3D stacked ICs
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.beginpage7.1
dc.source.conferenceIEEE International Test Conference - ITC
dc.source.conferencedate10/09/2013
dc.source.conferencelocationAnaheim, CA USA
imec.availabilityPublished - imec


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