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Impact of the on-chip and off-chip ESD protection network on transient-induced latchup in CMOS IC

dc.contributor.authorScholz, Mirko
dc.contributor.authorChen, Shih-Hung
dc.contributor.authorHellings, Geert
dc.contributor.authorLinten, Dimitri
dc.date.accessioned2021-10-21T11:48:32Z
dc.date.available2021-10-21T11:48:32Z
dc.date.issued2013-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23050
dc.sourceIIOimport
dc.titleImpact of the on-chip and off-chip ESD protection network on transient-induced latchup in CMOS IC
dc.typeProceedings paper
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.imecauthorHellings, Geert
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.source.peerreviewyes
dc.source.beginpage148
dc.source.endpage155
dc.source.conference35th Annual EOS/ESD Symposium
dc.source.conferencedate8/09/2013
dc.source.conferencelocationLas Vegas, NV USA
dc.identifier.urlIEEE Explore
imec.availabilityPublished - imec


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