Show simple item record

Bilayer graphene tunneling-FET for sub-0.2 V digital CMOS logic applications

dc.contributor.authorAgarwal Kumar, Tarun
dc.contributor.authorNourbakhsh, Amirhasan
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorRadu, Iuliana
dc.contributor.authorVerhelst, Marian
dc.contributor.authorDe Gendt, Stefan
dc.contributor.authorHeyns, Marc
dc.contributor.authorThean, Aaron
dc.date.accessioned2021-10-22T00:43:09Z
dc.date.available2021-10-22T00:43:09Z
dc.date.issued2014
dc.identifier.issn0741-3106
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23472
dc.sourceIIOimport
dc.titleBilayer graphene tunneling-FET for sub-0.2 V digital CMOS logic applications
dc.typeJournal article
dc.contributor.imecauthorRadu, Iuliana
dc.contributor.imecauthorVerhelst, Marian
dc.contributor.imecauthorDe Gendt, Stefan
dc.contributor.imecauthorHeyns, Marc
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecRadu, Iuliana::0000-0002-7230-7218
dc.contributor.orcidimecVerhelst, Marian::0000-0003-3495-9263
dc.contributor.orcidimecDe Gendt, Stefan::0000-0003-3775-3578
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1308
dc.source.endpage1310
dc.source.journalIEEE Electron Device Letters
dc.source.issue12
dc.source.volume35
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6936851
imec.availabilityPublished - open access


Files in this item

Thumbnail
Name:
29959.pdf
Size:
696.7Kb
Format:
PDF
View/open

This item appears in the following collection(s)

Show simple item record