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Bilayer graphene tunneling-FET for sub-0.2 V digital CMOS logic applications
Publication:
Bilayer graphene tunneling-FET for sub-0.2 V digital CMOS logic applications
Date
2014
Journal article
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Basic data
APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Agarwal Kumar, Tarun
;
Nourbakhsh, Amirhasan
;
Raghavan, Praveen
;
Radu, Iuliana
;
Verhelst, Marian
;
De Gendt, Stefan
;
Heyns, Marc
;
Thean, Aaron
Journal
IEEE Electron Device Letters
Abstract
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1994
since deposited on 2021-10-22
Acq. date: 2025-10-29
Citations
Metrics
Views
1994
since deposited on 2021-10-22
Acq. date: 2025-10-29
Citations