Publication:

Bilayer graphene tunneling-FET for sub-0.2 V digital CMOS logic applications

Date

2014
Journal article
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dc.contributor.authorAgarwal Kumar, Tarun
dc.contributor.authorNourbakhsh, Amirhasan
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorRadu, Iuliana
dc.contributor.authorVerhelst, Marian
dc.contributor.authorDe Gendt, Stefan
dc.contributor.authorHeyns, Marc
dc.contributor.authorThean, Aaron
dc.contributor.imecauthorRadu, Iuliana
dc.contributor.imecauthorVerhelst, Marian
dc.contributor.imecauthorDe Gendt, Stefan
dc.contributor.imecauthorHeyns, Marc
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecRadu, Iuliana::0000-0002-7230-7218
dc.contributor.orcidimecVerhelst, Marian::0000-0003-3495-9263
dc.contributor.orcidimecDe Gendt, Stefan::0000-0003-3775-3578
dc.date.accessioned2021-10-22T00:43:09Z
dc.date.available2021-10-22T00:43:09Z
dc.date.embargo9999-12-31
dc.date.issued2014
dc.identifier.issn0741-3106
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23472
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6936851
dc.source.beginpage1308
dc.source.endpage1310
dc.source.issue12
dc.source.journalIEEE Electron Device Letters
dc.source.volume35
dc.title

Bilayer graphene tunneling-FET for sub-0.2 V digital CMOS logic applications

dc.typeJournal article
dspace.entity.typePublication
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