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A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring

dc.contributor.authorAraga, Yuuki
dc.contributor.authorMiura, Ranto
dc.contributor.authorNagata, Makoto
dc.contributor.authorRoda Neve, Cesar
dc.contributor.authorDe Vos, Joeri
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorBeyne, Eric
dc.date.accessioned2021-10-22T00:43:47Z
dc.date.available2021-10-22T00:43:47Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23496
dc.sourceIIOimport
dc.titleA study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring
dc.typeProceedings paper
dc.contributor.imecauthorDe Vos, Joeri
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecDe Vos, Joeri::0000-0002-9332-9336
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage5
dc.source.conferenceElectronics System-Integration Technology Conference - ESTC
dc.source.conferencedate16/09/2014
dc.source.conferencelocationHelsinki Finland
imec.availabilityPublished - imec


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