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Wafer scale copper direct plating on thin PVD RuTa layers: a route to enable filling 30 nm features and below?

dc.contributor.authorArmini, Silvia
dc.contributor.authorEl-Mekki, Zaid
dc.contributor.authorNagar, Magi
dc.contributor.authorRadisic, Alex
dc.contributor.authorRuythooren, Wouter
dc.contributor.authorVereecken, Philippe
dc.date.accessioned2021-10-22T00:43:59Z
dc.date.available2021-10-22T00:43:59Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23501
dc.sourceIIOimport
dc.titleWafer scale copper direct plating on thin PVD RuTa layers: a route to enable filling 30 nm features and below?
dc.typeProceedings paper
dc.contributor.imecauthorArmini, Silvia
dc.contributor.imecauthorEl-Mekki, Zaid
dc.contributor.imecauthorRadisic, Alex
dc.contributor.imecauthorRuythooren, Wouter
dc.contributor.imecauthorVereecken, Philippe
dc.contributor.orcidimecArmini, Silvia::0000-0003-0578-3422
dc.contributor.orcidimecVereecken, Philippe::0000-0003-4115-0075
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage3
dc.source.endpage15
dc.source.conferenceProcessing, Materials, and Integration of Damascene and 3D Interconnects 5
dc.source.conferencedate28/10/2013
dc.source.conferencelocationSan Francisco, CA USA
dc.identifier.urlhttp://ecst.ecsdl.org/content/58/17/3.abstract
imec.availabilityPublished - open access
imec.internalnotesECS Transactions; Vol. 58, Issue 17


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