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Performance and perspectives of 0-level MEMS chip packages with vertical interconnects

dc.contributor.authorCherman, Vladimir
dc.contributor.authorPham, Nga
dc.contributor.authorSlabbekoorn, John
dc.contributor.authorFaes, Alessandro
dc.contributor.authorMargesin, Benno
dc.contributor.authorTilmans, Harrie
dc.date.accessioned2021-10-22T00:56:34Z
dc.date.available2021-10-22T00:56:34Z
dc.date.issued2014
dc.identifier.issn1551-4897
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23640
dc.sourceIIOimport
dc.titlePerformance and perspectives of 0-level MEMS chip packages with vertical interconnects
dc.typeJournal article
dc.contributor.imecauthorCherman, Vladimir
dc.contributor.imecauthorPham, Nga
dc.contributor.imecauthorSlabbekoorn, John
dc.contributor.imecauthorTilmans, Harrie
dc.contributor.orcidimecTilmans, Harrie::0000-0003-4240-4962
dc.source.peerreviewyes
dc.source.beginpage87
dc.source.endpage13
dc.source.journalJournal of Microelectronics and Electronic Packaging
dc.source.issue3
dc.source.volume11
dc.identifier.urlhttp://www.imaps.org/imapsstore/detail.aspx?ID=4013
imec.availabilityPublished - imec


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