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Metrology and inspection requirements for successful stacking of integrated circuits

dc.contributor.authorHalder, Sandip
dc.contributor.authorMiller, Andy
dc.contributor.authorVan Puymbroeck, Jan
dc.contributor.authorNieuborg, Nancy
dc.contributor.authorBeyne, Eric
dc.date.accessioned2021-10-22T01:49:29Z
dc.date.available2021-10-22T01:49:29Z
dc.date.issued2014
dc.identifier.issn0894-6507
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23900
dc.sourceIIOimport
dc.titleMetrology and inspection requirements for successful stacking of integrated circuits
dc.typeJournal article
dc.contributor.imecauthorHalder, Sandip
dc.contributor.imecauthorMiller, Andy
dc.contributor.imecauthorVan Puymbroeck, Jan
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecHalder, Sandip::0000-0002-6314-2685
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage370
dc.source.endpage376
dc.source.journalIEEE Transactions on Semiconductor Manufacturing
dc.source.issue3
dc.source.volume27
dc.identifier.urlhttp://ieeexplore.ieee.org/document/6869040/?arnumber=6869040
imec.availabilityPublished - open access


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