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Modelling and mitigation of time-zero variability in sub-16nm FinFET-based STT-MRAM memories

dc.contributor.authorHartmann, Matthias
dc.contributor.authorKukner, Halil
dc.contributor.authorAgrawal, Prashant
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorVan der Perre, Liesbet
dc.contributor.authorDehaene, Wim
dc.date.accessioned2021-10-22T01:51:24Z
dc.date.available2021-10-22T01:51:24Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23907
dc.sourceIIOimport
dc.titleModelling and mitigation of time-zero variability in sub-16nm FinFET-based STT-MRAM memories
dc.typeProceedings paper
dc.contributor.imecauthorHartmann, Matthias
dc.contributor.imecauthorAgrawal, Prashant
dc.contributor.imecauthorDehaene, Wim
dc.contributor.orcidimecHartmann, Matthias::0000-0001-6248-1151
dc.source.peerreviewyes
dc.source.beginpage243
dc.source.endpage244
dc.source.conference24th Great Lakes Symposium on VLSI - GLSVLSI
dc.source.conferencedate21/05/2014
dc.source.conferencelocationHouston USA
dc.identifier.urlhttp://dl.acm.org/citation.cfm?id=2591573
imec.availabilityPublished - imec


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