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A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction

dc.contributor.authorHershberg, Benjamin
dc.contributor.authorRaczkowski, Kuba
dc.contributor.authorVaesen, Kristof
dc.contributor.authorCraninckx, Jan
dc.date.accessioned2021-10-22T01:55:27Z
dc.date.available2021-10-22T01:55:27Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23924
dc.sourceIIOimport
dc.titleA 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction
dc.typeProceedings paper
dc.contributor.imecauthorHershberg, Benjamin
dc.contributor.imecauthorVaesen, Kristof
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.orcidimecVaesen, Kristof::0000-0001-9971-3593
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage83
dc.source.endpage86
dc.source.conference40th European Solid-State Circuits Conference - ESSCIRC
dc.source.conferencedate22/09/2014
dc.source.conferencelocationVenice Italy
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6942027
imec.availabilityPublished - open access


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