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High yield fabrication process for 3D-stacked ultra-thin chip packages using photo-definable polyimide and symmetry in packages

dc.contributor.authorPriyabadini, Swarnakamal
dc.contributor.authorSterken, Tom
dc.contributor.authorCauwe, Maarten
dc.contributor.authorVan Hoorebeke, Luc
dc.contributor.authorVanfleteren, Jan
dc.date.accessioned2021-10-22T04:50:43Z
dc.date.available2021-10-22T04:50:43Z
dc.date.issued2014
dc.identifier.issn2156-3950
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24398
dc.sourceIIOimport
dc.titleHigh yield fabrication process for 3D-stacked ultra-thin chip packages using photo-definable polyimide and symmetry in packages
dc.typeJournal article
dc.contributor.imecauthorSterken, Tom
dc.contributor.imecauthorCauwe, Maarten
dc.contributor.imecauthorVanfleteren, Jan
dc.contributor.orcidimecCauwe, Maarten::0000-0002-6413-998X
dc.contributor.orcidimecVanfleteren, Jan::0000-0002-9654-7304
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage158
dc.source.endpage167
dc.source.journalIEEE Transactions on Components, Packaging and Manufacturing Technology
dc.source.issue1
dc.source.volume4
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6657822
imec.availabilityPublished - open access


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