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Optimized design of a Si-cap layer in strained-SiGe channel p-MOSFETs based on computational and experimental approaches

dc.contributor.authorSato-Iwanaga, Junko
dc.contributor.authorInoue, Akira
dc.contributor.authorSorada, Haruyuki
dc.contributor.authorTakagi, Takeshi
dc.contributor.authorRothschild, Aude
dc.contributor.authorLoo, Roger
dc.contributor.authorBiesemans, Serge
dc.contributor.authorIto, Choshu
dc.contributor.authorLiu, Yang
dc.contributor.authorDutton, Robert W.
dc.contributor.authorTsuchiya, Hideaki
dc.date.accessioned2021-10-22T05:29:36Z
dc.date.available2021-10-22T05:29:36Z
dc.date.issued2014
dc.identifier.issn0038-1101
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24482
dc.sourceIIOimport
dc.titleOptimized design of a Si-cap layer in strained-SiGe channel p-MOSFETs based on computational and experimental approaches
dc.typeJournal article
dc.contributor.imecauthorLoo, Roger
dc.contributor.imecauthorBiesemans, Serge
dc.contributor.orcidimecLoo, Roger::0000-0003-3513-6058
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage8
dc.source.journalSolid-State Electronics
dc.source.volume91
dc.identifier.urlhttp://dx.doi.org/10.1016/j.sse.2013.09.010
imec.availabilityPublished - imec


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