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Optimized process simulation of USJ for HKMG DRAM periphery transistors

dc.contributor.authorSpessot, Alessio
dc.contributor.authorCaillat, Christian
dc.contributor.authorRitzenthaler, Romain
dc.contributor.authorSchram, Tom
dc.contributor.authorFazan, Pierre
dc.date.accessioned2021-10-22T06:05:56Z
dc.date.available2021-10-22T06:05:56Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24557
dc.sourceIIOimport
dc.titleOptimized process simulation of USJ for HKMG DRAM periphery transistors
dc.typeProceedings paper
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorRitzenthaler, Romain
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorFazan, Pierre
dc.contributor.orcidimecRitzenthaler, Romain::0000-0002-8615-3272
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage4
dc.source.conferenceIEEE Workshop On Microelectronics And Electron Devices - WMED
dc.source.conferencedate18/04/2014
dc.source.conferencelocationBoise, ID USA
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6818722&queryText%3DUSJ+for+HKMG+DRAM+periphery+transistors
imec.availabilityPublished - open access


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