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A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS

dc.contributor.authorSzortyka, Viki
dc.contributor.authorShi, Qixian
dc.contributor.authorRaczkowski, Kuba
dc.contributor.authorParvais, Bertrand
dc.contributor.authorKuijk, Maarten
dc.contributor.authorWambacq, Piet
dc.date.accessioned2021-10-22T06:18:04Z
dc.date.available2021-10-22T06:18:04Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24582
dc.sourceIIOimport
dc.titleA 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS
dc.typeProceedings paper
dc.contributor.imecauthorShi, Qixian
dc.contributor.imecauthorParvais, Bertrand
dc.contributor.imecauthorWambacq, Piet
dc.contributor.orcidimecParvais, Bertrand::0000-0003-0769-7069
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.source.peerreviewyes
dc.source.beginpage366
dc.source.endpage367
dc.source.conferenceIEEE International Solid-State Circuits Conference - ISSCC
dc.source.conferencedate9/02/2014
dc.source.conferencelocationSan Francisco, CA USA
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6757472&queryText%3Dszortyka
imec.availabilityPublished - imec


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