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Quality versus cost analysis for 3D stacked ICs

dc.contributor.authorTaouil, Mottaqiallah
dc.contributor.authorHamdioui, Said
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-22T06:27:18Z
dc.date.available2021-10-22T06:27:18Z
dc.date.issued2014-04
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24601
dc.sourceIIOimport
dc.titleQuality versus cost analysis for 3D stacked ICs
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage6
dc.source.conferenceIEEE VLSI Test Symposium - VTS
dc.source.conferencedate13/04/2014
dc.source.conferencelocationNapa, CA USA
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6818763
imec.availabilityPublished - imec


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