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Interconnect test for 3D stacked memory-on-logic

dc.contributor.authorTaouil, Mottaqiallah
dc.contributor.authorMasadeh, Mahmoud
dc.contributor.authorHamdioui, Said
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-22T06:28:09Z
dc.date.available2021-10-22T06:28:09Z
dc.date.issued2014-03
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24603
dc.sourceIIOimport
dc.titleInterconnect test for 3D stacked memory-on-logic
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage6
dc.source.conferenceDesign, Automation and Test in Europe Conference - DATE
dc.source.conferencedate24/03/2014
dc.source.conferencelocationDresden Germany
dc.identifier.urlhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6800340&tag=1tp=&arnumber=6800340
imec.availabilityPublished - imec


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