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On the modelling of Border trap admittance in high-K/III-V devices

dc.contributor.authorVais, Abhitosh
dc.date.accessioned2021-10-22T06:49:15Z
dc.date.available2021-10-22T06:49:15Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24646
dc.sourceIIOimport
dc.titleOn the modelling of Border trap admittance in high-K/III-V devices
dc.typeMeeting abstract
dc.contributor.imecauthorVais, Abhitosh
dc.contributor.orcidimecVais, Abhitosh::0000-0002-0317-7720
dc.source.peerreviewno
dc.source.beginpagena
dc.source.conferenceIEEE Semiconductor Interfaces Specialist Conference - SISC
dc.source.conferencedate10/12/2014
dc.source.conferencelocationSan Diego, CA USA
imec.availabilityPublished - imec


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