dc.contributor.author | Vandewalle, Boris | |
dc.contributor.author | Chava, Bharani | |
dc.contributor.author | Sakhare, Sushil | |
dc.contributor.author | Ryckaert, Julien | |
dc.contributor.author | Dusa, Mircea | |
dc.date.accessioned | 2021-10-22T07:31:16Z | |
dc.date.available | 2021-10-22T07:31:16Z | |
dc.date.issued | 2014 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/24732 | |
dc.source | IIOimport | |
dc.title | Design technology co-optimization for a robust 10nm solution for logic design and Sram | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Ryckaert, Julien | |
dc.contributor.imecauthor | Dusa, Mircea | |
dc.date.embargo | 9999-12-31 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 90530Q | |
dc.source.conference | Design-Process-Technology Co-Optimization for Manufacturability VIII | |
dc.source.conferencedate | 25/02/2014 | |
dc.source.conferencelocation | San Jose, CA USA | |
dc.identifier.url | http://spie.org/Publications/Proceedings/Paper/10.1117/12.2048079 | |
imec.availability | Published - open access | |
imec.internalnotes | Proceedings of SPIE; Vol. 9053 | |