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N10 logic patterning

dc.contributor.authorXu, Kaidong
dc.contributor.authorTao, Zheng
dc.contributor.authorHody, Hubert
dc.contributor.authorMannaert, Geert
dc.contributor.authorKunnen, Eddy
dc.contributor.authorMao, Ming
dc.contributor.authorLazzarino, Frederic
dc.contributor.authorDecoster, Stefan
dc.date.accessioned2021-10-22T08:36:13Z
dc.date.available2021-10-22T08:36:13Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24852
dc.sourceIIOimport
dc.titleN10 logic patterning
dc.typeMeeting abstract
dc.contributor.imecauthorTao, Zheng
dc.contributor.imecauthorHody, Hubert
dc.contributor.imecauthorMannaert, Geert
dc.contributor.imecauthorMao, Ming
dc.contributor.imecauthorLazzarino, Frederic
dc.contributor.imecauthorDecoster, Stefan
dc.contributor.orcidimecLazzarino, Frederic::0000-0001-7961-9727
dc.contributor.orcidimecDecoster, Stefan::0000-0003-1162-9288
dc.source.peerreviewyes
dc.source.conferenceChina Semiconductor Technology International Conference. Symposium III: Dry & Wet Etch and Cleaning
dc.source.conferencedate16/03/2014
dc.source.conferencelocationShanghai China
imec.availabilityPublished - imec


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