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System-level assessment and area performance evaluation of spin wave logic circuits

dc.contributor.authorZografos, Odysseas
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorAmaru, Luca
dc.contributor.authorSoree, Bart
dc.contributor.authorLauwereins, Rudy
dc.date.accessioned2021-10-22T09:01:59Z
dc.date.available2021-10-22T09:01:59Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24897
dc.sourceIIOimport
dc.titleSystem-level assessment and area performance evaluation of spin wave logic circuits
dc.typeProceedings paper
dc.contributor.imecauthorZografos, Odysseas
dc.contributor.imecauthorSoree, Bart
dc.contributor.imecauthorLauwereins, Rudy
dc.contributor.orcidimecZografos, Odysseas::0000-0002-9998-8009
dc.contributor.orcidimecSoree, Bart::0000-0002-4157-1956
dc.contributor.orcidimecLauwereins, Rudy::0000-0002-3861-0168
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage25
dc.source.endpage30
dc.source.conferenceIEEE/ACM International Symposium on Nanoscale Architectures - NANOARCH
dc.source.conferencedate8/07/2014
dc.source.conferencelocationParis France
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6880475
imec.availabilityPublished - open access


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