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Stack and topography verification as an enabler for computational metrology target design

dc.contributor.authorAdel, Michael E.
dc.contributor.authorTarshish-Shapir, Inna
dc.contributor.authorGready, David
dc.contributor.authorGhinovker, Mark
dc.contributor.authorDror, Chen
dc.contributor.authorGodny, Stephane
dc.date.accessioned2021-10-22T18:29:50Z
dc.date.available2021-10-22T18:29:50Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24914
dc.sourceIIOimport
dc.titleStack and topography verification as an enabler for computational metrology target design
dc.typeProceedings paper
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage94240D
dc.source.conferenceMetrology, Inspection, and Process Control for Microlithography XXIX
dc.source.conferencedate22/02/2015
dc.source.conferencelocationSan Jose, CA USA
dc.identifier.urlhttp://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=2272964
imec.availabilityPublished - open access
imec.internalnotesProceedings of SPIE; Vol. 9424


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