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Robust optimization of test-access architectures under realistic scenarios

dc.contributor.authorDeutsch, Sergej
dc.contributor.authorChakrabarty, Krishnendu
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-22T19:00:41Z
dc.date.available2021-10-22T19:00:41Z
dc.date.issued2015-11
dc.identifier.issn0278-0070
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25198
dc.sourceIIOimport
dc.titleRobust optimization of test-access architectures under realistic scenarios
dc.typeJournal article
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.beginpage1873
dc.source.endpage1884
dc.source.journalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
dc.source.issue11
dc.source.volume34
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7105888
imec.availabilityPublished - imec


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