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Impact of device and interconnect process variability on clock distribution

dc.contributor.authorFievet, Nathalie
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorBaert, Rogier
dc.contributor.authorRobert, Frederic
dc.contributor.authorMercha, Abdelkarim
dc.contributor.authorVerkest, Diederik
dc.contributor.authorThean, Aaron
dc.date.accessioned2021-10-22T19:14:55Z
dc.date.available2021-10-22T19:14:55Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25270
dc.sourceIIOimport
dc.titleImpact of device and interconnect process variability on clock distribution
dc.typeProceedings paper
dc.contributor.imecauthorBaert, Rogier
dc.contributor.imecauthorMercha, Abdelkarim
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecMercha, Abdelkarim::0000-0002-2174-6958
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage4
dc.source.conferenceInternational Conference on IC Design & Technology - ICICDT
dc.source.conferencedate1/06/2015
dc.source.conferencelocationLeuven Belgium
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7165895
imec.availabilityPublished - imec


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