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Si-cap-free SiGe p-channel Fin FETS and gate-all-around transistors in a replacement metal gate Process: interface trap density reduction and performance improvement by high-pressure deuterium anneal

dc.contributor.authorMertens, Hans
dc.contributor.authorRitzenthaler, Romain
dc.contributor.authorArimura, Hiroaki
dc.contributor.authorFranco, Jacopo
dc.contributor.authorSebaai, Farid
dc.contributor.authorHikavyy, Andriy
dc.contributor.authorPawlak, Bartek
dc.contributor.authorMachkaoutsan, Vladimir
dc.contributor.authorDevriendt, Katia
dc.contributor.authorTsvetanova, Diana
dc.contributor.authorMilenin, Alexey
dc.contributor.authorWitters, Liesbeth
dc.contributor.authorDangol, Anish
dc.contributor.authorVancoille, Eric
dc.contributor.authorBender, Hugo
dc.contributor.authorBadaroglu, Mustafa
dc.contributor.authorHolsteyns, Frank
dc.contributor.authorBarla, Kathy
dc.contributor.authorMocuta, Dan
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorThean, Aaron
dc.date.accessioned2021-10-22T21:04:26Z
dc.date.available2021-10-22T21:04:26Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25641
dc.sourceIIOimport
dc.titleSi-cap-free SiGe p-channel Fin FETS and gate-all-around transistors in a replacement metal gate Process: interface trap density reduction and performance improvement by high-pressure deuterium anneal
dc.typeProceedings paper
dc.contributor.imecauthorMertens, Hans
dc.contributor.imecauthorRitzenthaler, Romain
dc.contributor.imecauthorArimura, Hiroaki
dc.contributor.imecauthorFranco, Jacopo
dc.contributor.imecauthorSebaai, Farid
dc.contributor.imecauthorHikavyy, Andriy
dc.contributor.imecauthorPawlak, Bartek
dc.contributor.imecauthorMachkaoutsan, Vladimir
dc.contributor.imecauthorDevriendt, Katia
dc.contributor.imecauthorTsvetanova, Diana
dc.contributor.imecauthorMilenin, Alexey
dc.contributor.imecauthorWitters, Liesbeth
dc.contributor.imecauthorDangol, Anish
dc.contributor.imecauthorVancoille, Eric
dc.contributor.imecauthorBender, Hugo
dc.contributor.imecauthorBadaroglu, Mustafa
dc.contributor.imecauthorHolsteyns, Frank
dc.contributor.imecauthorBarla, Kathy
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecRitzenthaler, Romain::0000-0002-8615-3272
dc.contributor.orcidimecFranco, Jacopo::0000-0002-7382-8605
dc.contributor.orcidimecHikavyy, Andriy::0000-0002-8201-075X
dc.contributor.orcidimecDevriendt, Katia::0000-0002-0662-7926
dc.contributor.orcidimecMilenin, Alexey::0000-0003-0747-0462
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage142
dc.source.endpage143
dc.source.conferenceSymposium on VLSI Technology
dc.source.conferencedate15/06/2015
dc.source.conferencelocationKyoto Japan
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7223654
imec.availabilityPublished - open access


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