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Study of hysteresis in vertical Ge-source heterojunction tunnel-FETs at low temperature

dc.contributor.authorNeves Souza, Felipe
dc.contributor.authorAgopian, Paula
dc.contributor.authorMartino, Joao
dc.contributor.authorVandooren, Anne
dc.contributor.authorRooyackers, Rita
dc.contributor.authorSimoen, Eddy
dc.contributor.authorThean, Aaron
dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-22T21:22:52Z
dc.date.available2021-10-22T21:22:52Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25691
dc.sourceIIOimport
dc.titleStudy of hysteresis in vertical Ge-source heterojunction tunnel-FETs at low temperature
dc.typeProceedings paper
dc.contributor.imecauthorVandooren, Anne
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecVandooren, Anne::0000-0002-2412-0176
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.source.peerreviewyes
dc.source.beginpage179
dc.source.endpage185
dc.source.conferenceAdvanced CMOS-Compatible Semiconductor Devices 17
dc.source.conferencedate24/05/2015
dc.source.conferencelocationChicago, IL USA
dc.identifier.urlhttp://ecst.ecsdl.org/content/66/5/179.abstract
imec.availabilityPublished - imec
imec.internalnotesECS Transactions; Vol. 66, Issue 5


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