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Hierarchical design flow aspects in the implementation of a 10+ Gbps LDPC decoder

dc.contributor.authorRykunov, Maxim
dc.date.accessioned2021-10-22T22:26:54Z
dc.date.available2021-10-22T22:26:54Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25847
dc.sourceIIOimport
dc.titleHierarchical design flow aspects in the implementation of a 10+ Gbps LDPC decoder
dc.typeProceedings paper
dc.contributor.imecauthorRykunov, Maxim
dc.contributor.orcidimecRykunov, Maxim::0000-0001-9568-8239
dc.source.peerreviewyes
dc.source.conferenceCadence User Conference - CNDlive
dc.source.conferencedate27/04/2015
dc.source.conferencelocationMünchen Germany
imec.availabilityPublished - imec


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