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Vertical nanowire TFET diameter influence on intrinsic voltage gain for different inversion conditions

dc.contributor.authorSivieri, V.B.
dc.contributor.authorBordallo, Caio
dc.contributor.authorAgopian, Paula G.D.
dc.contributor.authorMartino, Joao Antonio
dc.contributor.authorRooyackers, Rita
dc.contributor.authorVandooren, Anne
dc.contributor.authorSimoen, Eddy
dc.contributor.authorThean, Aaron
dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-22T22:59:52Z
dc.date.available2021-10-22T22:59:52Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25922
dc.sourceIIOimport
dc.titleVertical nanowire TFET diameter influence on intrinsic voltage gain for different inversion conditions
dc.typeProceedings paper
dc.contributor.imecauthorVandooren, Anne
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecVandooren, Anne::0000-0002-2412-0176
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.source.peerreviewyes
dc.source.beginpage187
dc.source.endpage192
dc.source.conferenceAdvanced CMOS-Compatible Semiconductor Devices 17
dc.source.conferencedate24/05/2015
dc.source.conferencelocationChicago, IL USA
dc.identifier.urlhttp://ecst.ecsdl.org/content/66/5/187.abstract
imec.availabilityPublished - imec
imec.internalnotesECS Transactions; Vol. 66, Issue 5


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