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Post-bond interconnect test and diagnosis for 3D memory stacked on logic

dc.contributor.authorTaouil, Mottaqiallah
dc.contributor.authorMasadeh, Mahmoud
dc.contributor.authorHamdioui, Said
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-22T23:28:24Z
dc.date.available2021-10-22T23:28:24Z
dc.date.issued2015-11
dc.identifier.issn0278-0070
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25984
dc.sourceIIOimport
dc.titlePost-bond interconnect test and diagnosis for 3D memory stacked on logic
dc.typeJournal article
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.beginpage1860
dc.source.endpage1872
dc.source.journalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
dc.source.issue11
dc.source.volume34
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7105883
imec.availabilityPublished - imec


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