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A methodology for efficient estimation of switching activity in sequential logic circuits

dc.contributor.authorMonteiro, J.
dc.contributor.authorDevadas, S.
dc.contributor.authorLin, Bill
dc.date.accessioned2021-09-29T12:44:11Z
dc.date.available2021-09-29T12:44:11Z
dc.date.issued1994
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/265
dc.sourceIIOimport
dc.titleA methodology for efficient estimation of switching activity in sequential logic circuits
dc.typeProceedings paper
dc.source.peerreviewno
dc.source.beginpage12
dc.source.endpage17
dc.source.conference31st Design Automation Conference. 31st DAC Proceedings; June 6-10 1994; San Diego, Calif., USA.
imec.availabilityPublished - imec


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