Show simple item record

Device/system performance modeling of stacked lateral NWFET logic

dc.contributor.authorHuang, Victor
dc.contributor.authorPang, Chenyun
dc.contributor.authorYakimets, Dmitry
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorNaaemi, Azad
dc.date.accessioned2021-10-23T11:24:38Z
dc.date.available2021-10-23T11:24:38Z
dc.date.issued2016
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26754
dc.sourceIIOimport
dc.titleDevice/system performance modeling of stacked lateral NWFET logic
dc.typeProceedings paper
dc.contributor.imecauthorYakimets, Dmitry
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage215
dc.source.endpage220
dc.source.conference17th International Symposium on Quality Electronic Design - ISQED
dc.source.conferencedate15/04/2016
dc.source.conferencelocationSanta Clara, CA USA
dc.identifier.urlhttp://ieeexplore.ieee.org/document/7479203/?arnumber=7479203
imec.availabilityPublished - open access


Files in this item

Thumbnail
Name:
33348.pdf
Size:
549.3Kb
Format:
PDF
View/open

This item appears in the following collection(s)

Show simple item record