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Imaging semiconductor patterns at N10 logic node with a high-throughput multi-beam SEM

dc.contributor.authorNeumann, J.T.
dc.contributor.authorGaraboski, T.
dc.contributor.authorHalder, Sandip
dc.contributor.authorLeray, Philippe
dc.contributor.authorGarreis, R.
dc.contributor.authorZeidler, D.
dc.date.accessioned2021-10-23T13:14:13Z
dc.date.available2021-10-23T13:14:13Z
dc.date.issued2016
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/27073
dc.sourceIIOimport
dc.titleImaging semiconductor patterns at N10 logic node with a high-throughput multi-beam SEM
dc.typeMeeting abstract
dc.contributor.imecauthorHalder, Sandip
dc.contributor.imecauthorLeray, Philippe
dc.contributor.orcidimecHalder, Sandip::0000-0002-6314-2685
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage3B3
dc.source.conference60th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication - EIPBN
dc.source.conferencedate31/05/2016
dc.source.conferencelocationPittsburgh, PA USA
imec.availabilityPublished - open access


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