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An analytical model of MOS admittance for border trap density extraction in high-k dielectrics of III-V MOS devices

dc.contributor.authorVais, Abhitosh
dc.contributor.authorMartens, Koen
dc.contributor.authorLin, Dennis
dc.contributor.authorMocuta, Anda
dc.contributor.authorCollaert, Nadine
dc.contributor.authorThean, Aaron
dc.contributor.authorDe Meyer, Kristin
dc.date.accessioned2021-10-23T15:49:16Z
dc.date.available2021-10-23T15:49:16Z
dc.date.issued2016
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/27425
dc.sourceIIOimport
dc.titleAn analytical model of MOS admittance for border trap density extraction in high-k dielectrics of III-V MOS devices
dc.typeJournal article
dc.contributor.imecauthorVais, Abhitosh
dc.contributor.imecauthorMartens, Koen
dc.contributor.imecauthorLin, Dennis
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorThean, Aaron
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.orcidimecVais, Abhitosh::0000-0002-0317-7720
dc.contributor.orcidimecMartens, Koen::0000-0001-7135-5536
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage4707
dc.source.endpage4713
dc.source.journalIEEE Transactions on Electron Devices
dc.source.issue12
dc.source.volume63
dc.identifier.urlhttp://ieeexplore.ieee.org/document/7731244/
imec.availabilityPublished - open access


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