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Challenges and opportunities of vertical FET devices using 3D circuit design layouts

dc.contributor.authorVeloso, Anabela
dc.contributor.authorHuynh Bao, Trong
dc.contributor.authorRosseel, Erik
dc.contributor.authorParaschiv, Vasile
dc.contributor.authorDevriendt, Katia
dc.contributor.authorVecchio, Emma
dc.contributor.authorDelvaux, Christie
dc.contributor.authorChan, BT
dc.contributor.authorErcken, Monique
dc.contributor.authorTao, Zheng
dc.contributor.authorLi, Waikin
dc.contributor.authorAltamirano Sanchez, Efrain
dc.contributor.authorVersluijs, Janko
dc.contributor.authorBrus, Stephan
dc.contributor.authorMatagne, Philippe
dc.contributor.authorWaldron, Niamh
dc.contributor.authorRyckaert, Julien
dc.contributor.authorMocuta, Dan
dc.contributor.authorCollaert, Nadine
dc.date.accessioned2021-10-23T16:31:48Z
dc.date.available2021-10-23T16:31:48Z
dc.date.issued2016
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/27513
dc.sourceIIOimport
dc.titleChallenges and opportunities of vertical FET devices using 3D circuit design layouts
dc.typeProceedings paper
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorRosseel, Erik
dc.contributor.imecauthorParaschiv, Vasile
dc.contributor.imecauthorDevriendt, Katia
dc.contributor.imecauthorVecchio, Emma
dc.contributor.imecauthorDelvaux, Christie
dc.contributor.imecauthorChan, BT
dc.contributor.imecauthorErcken, Monique
dc.contributor.imecauthorTao, Zheng
dc.contributor.imecauthorLi, Waikin
dc.contributor.imecauthorAltamirano Sanchez, Efrain
dc.contributor.imecauthorVersluijs, Janko
dc.contributor.imecauthorBrus, Stephan
dc.contributor.imecauthorMatagne, Philippe
dc.contributor.imecauthorWaldron, Niamh
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.orcidimecDevriendt, Katia::0000-0002-0662-7926
dc.contributor.orcidimecChan, BT::0000-0003-2890-0388
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage3
dc.source.conferenceIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - S3S
dc.source.conferencedate10/10/2016
dc.source.conferencelocationSan Francisco, CA USA
dc.identifier.urlhttp://ieeexplore.ieee.org/document/7804409/
imec.availabilityPublished - imec


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