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Back gate voltage influence on the LDD SOI NMOSFET series resistance extraction from 150 to 300 K

dc.contributor.authorNicolett, A. S.
dc.contributor.authorMartino, Joao Antonio
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, C.
dc.date.accessioned2021-10-01T08:33:30Z
dc.date.available2021-10-01T08:33:30Z
dc.date.issued1998
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/2804
dc.sourceIIOimport
dc.titleBack gate voltage influence on the LDD SOI NMOSFET series resistance extraction from 150 to 300 K
dc.typeOral presentation
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.source.peerreviewno
dc.source.conferenceNATO Advanced Research Workshop on "Perspectives, Sciences and Technologies of Novel Silicon-on-Insulator Devices"; 12-15 Octobe
dc.source.conferencelocation
imec.availabilityPublished - imec


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