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Vertical M1 routing-aware detailed placement for congestion and wirelength reduction in sub-10nm nodes.

dc.contributor.authorDebacker, Peter
dc.contributor.authorHan, Kwangsoo
dc.contributor.authorKahng, Andrew
dc.contributor.authorLee, Hyein
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorWang, Lutong
dc.date.accessioned2021-10-24T04:02:39Z
dc.date.available2021-10-24T04:02:39Z
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/28185
dc.sourceIIOimport
dc.titleVertical M1 routing-aware detailed placement for congestion and wirelength reduction in sub-10nm nodes.
dc.typeProceedings paper
dc.contributor.imecauthorDebacker, Peter
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.conference54th ACM/EDAC/IEEE Design Automation Conference - DAC
dc.source.conferencedate18/06/2016
dc.source.conferencelocationAustin, TX USA
dc.identifier.urlhttps://dl.acm.org/citation.cfm?doid=3061639.3062338
imec.availabilityPublished - open access


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