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Impact of the combination of stress buffer layer and wafer level underfill on 3D IC assembly using thermal compression bonding

dc.contributor.authorDuval, Fabrice
dc.contributor.authorWang, Teng
dc.contributor.authorBex, Pieter
dc.contributor.authorLofrano, Melina
dc.contributor.authorRebibis, Kenneth June
dc.contributor.authorSleeckx, Erik
dc.contributor.authorBeyne, Eric
dc.contributor.authorGerets, Carine
dc.date.accessioned2021-10-24T04:32:13Z
dc.date.available2021-10-24T04:32:13Z
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/28295
dc.sourceIIOimport
dc.titleImpact of the combination of stress buffer layer and wafer level underfill on 3D IC assembly using thermal compression bonding
dc.typeProceedings paper
dc.contributor.imecauthorDuval, Fabrice
dc.contributor.imecauthorBex, Pieter
dc.contributor.imecauthorLofrano, Melina
dc.contributor.imecauthorRebibis, Kenneth June
dc.contributor.imecauthorSleeckx, Erik
dc.contributor.imecauthorBeyne, Eric
dc.contributor.imecauthorGerets, Carine
dc.contributor.orcidimecBex, Pieter::0000-0003-0896-2514
dc.contributor.orcidimecSleeckx, Erik::0000-0003-2560-6132
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage7
dc.source.conference21st European Microelectronics and Packaging Conference - EMPC
dc.source.conferencedate10/09/2017
dc.source.conferencelocationWarsaw Poland
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8346836
imec.availabilityPublished - open access


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