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Test and design-for-test of 3D-stacked ICs

dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-24T08:46:29Z
dc.date.available2021-10-24T08:46:29Z
dc.date.issued2017-12
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/28919
dc.sourceIIOimport
dc.titleTest and design-for-test of 3D-stacked ICs
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewno
dc.source.conferenceAdvanced Testing Technology Seminar
dc.source.conferencedate13/12/2017
dc.source.conferencelocationNanjing China
imec.availabilityPublished - imec


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