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On the hot-carrier-induced post-stress interface trap generation in n-channel MOS transistors

dc.contributor.authorBellens, Rudi
dc.contributor.authorDe Schrijver, Erik
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorHeremans, Paul
dc.contributor.authorMaes, Herman
dc.date.accessioned2021-09-29T12:39:45Z
dc.date.available2021-09-29T12:39:45Z
dc.date.issued1994
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/28
dc.sourceIIOimport
dc.titleOn the hot-carrier-induced post-stress interface trap generation in n-channel MOS transistors
dc.typeJournal article
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.imecauthorHeremans, Paul
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage413
dc.source.endpage419
dc.source.journalIEEE Transactions on Electron Devices
dc.source.issue3
dc.source.volume41
imec.availabilityPublished - open access


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