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Majority logic synthesis

dc.contributor.authorAmarù, Luca
dc.contributor.authorTesta, Eleonora
dc.contributor.authorCouceiro, Miguel
dc.contributor.authorZografos, Odysseas
dc.contributor.authorDe Micheli, Giovanni
dc.contributor.authorSoeken, Mathias
dc.date.accessioned2021-10-25T16:32:42Z
dc.date.available2021-10-25T16:32:42Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/30116
dc.sourceIIOimport
dc.titleMajority logic synthesis
dc.typeProceedings paper
dc.contributor.imecauthorTesta, Eleonora
dc.contributor.imecauthorZografos, Odysseas
dc.contributor.orcidimecZografos, Odysseas::0000-0002-9998-8009
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage6
dc.source.conference2018 IEEE/ACM International Conference on Computer-Aided Design - ICCAD
dc.source.conferencedate5/11/2018
dc.source.conferencelocationSan Diego, CA USA
imec.availabilityPublished - open access


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