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Pillar patterning of Silicon / III-V vertical nanowire FET for 7nm node and beyond

dc.contributor.authorChan, BT
dc.contributor.authorTao, Zheng
dc.contributor.authorAltamirano Sanchez, Efrain
dc.contributor.authorVeloso, Anabela
dc.contributor.authorde Marneffe, Jean-Francois
dc.contributor.authorSingh, Arjun
dc.date.accessioned2021-10-25T17:08:27Z
dc.date.available2021-10-25T17:08:27Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/30387
dc.sourceIIOimport
dc.titlePillar patterning of Silicon / III-V vertical nanowire FET for 7nm node and beyond
dc.typeMeeting abstract
dc.contributor.imecauthorChan, BT
dc.contributor.imecauthorTao, Zheng
dc.contributor.imecauthorAltamirano Sanchez, Efrain
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorde Marneffe, Jean-Francois
dc.contributor.imecauthorSingh, Arjun
dc.contributor.orcidimecChan, BT::0000-0003-2890-0388
dc.source.peerreviewyes
dc.source.conference31st International Microprocesses and Nanotechnology Conference
dc.source.conferencedate13/11/2018
dc.source.conferencelocationHiroshima Japan
imec.availabilityPublished - imec


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